Beezly's Blog

With Intel and AMD announcing the release of their multi-core CPUs, this article at Slashdot (or rather the comments underneath) started me on a bit of an internal rant.

Why don’t people get that Intel’s x86 implementation SUCKS and that by implementing more cores on the CPU, Intel are pretty much guaranteed to make the performance of SMP configurations even worse than they are today. Maybe this is why they’ve only announced Desktop (ie, single CPU) chips so far.

Here’s how it works…

AMD Opteron’s CPUs have memory controller on the chip itself. As you increase the number of CPUs in the box, you are increasing total memory bandwidth by the same amount (assuming you are populating the CPUs with memory too, you’d be insane not to!). Therefore memory bandwidth per core scales O(1) (I shudder as my memories of an Analysis of Algorithms course come back).

Intel’s CPUs have the memory controller located on the Northbridge. There is one Northbridge per box (unless you have a very specialised NUMA box). As you add CPUs, the memory bandwidth stays the same, but the number of cores increases. Therefore memory bandwidth per core scales O(1/n) – not good.

Adding multicore CPUs has the following effect on Opteron. There is still only 1 memory controller per CPU, but multiple cores. Memory bandwith per CPU (ie both cores) scales (compared to the single-core model) O(1/2).

Adding multicore CPUs has the following effect on Intel multicore. There is one north bridge, but multiple cores. Memory bandwidth per CPU scales O(1/2n) – that’s just moved from not good to AWFUL.

If I hear another Intel fanboy harp on about how wonderful Intel’s multicore will be, I’m going to EXPLODE!